Work Experience

Google, Senior Staff Software Engineer · Mountain View, CA, USA · May 2017 – current

• Brain / Google DeepMind (2021–)
  • Pathways: distributed systems for large-scale machine learning
  • Infrastructure for large ML model inference
  • Gemini Infra core contributor
• System Infrastructure (2017–2021)
  • Hardware/software co-design for datacenters
  • System optimization for large-scale data analytics workloads
  • Using machine learning to optimize systems

Google, Software Engineering Intern · Mountain View, CA, USA · Jun. 2016 – Sep. 2016

• Mentor: Dr. Niket Agarwal
• Evaluated the potential of non-volatile memory technologies for datacenter applications

Oracle Labs, Research Assistant · Belmont, CA, USA · Oct. 2015 – Feb. 2016

• Mentors: Dr. Hassan Chafi and Dr. Sungpack Hong
• Characterized and optimized analytic applications on a custom-built, rack-scale server architecture

Seoul National University, Graduate Research Assistant · Seoul, Republic of Korea · Mar. 2011 – Feb. 2017

• Advisor: Prof. Kiyoung Choi
• Developed architectures and programming models for high-performance, energy-efficient memory systems
• Devised efficient algorithms for automatic custom instruction identification

Seoul National University, Undergraduate Research Assistant · Seoul, Republic of Korea · Mar. 2010 – Feb. 2011

• Advisor: Prof. Kiyoung Choi
• Devised a fast algorithm for automatic custom instruction identification

Education

Seoul National University · Seoul, Republic of Korea · Mar. 2011 – Feb. 2017

• Ph.D. in Electrical Engineering and Computer Science
• Dissertation: Architectural Techniques for Memory Systems based on Emerging Memory Technologies
• Advisor: Prof. Kiyoung Choi

Seoul National University · Seoul, Republic of Korea · Mar. 2007 – Feb. 2011

• Bachelor of Science in Electrical Engineering (minor: Computer Science and Engineering)
• Thesis: A Polynomial-Time Custom Instruction Identification Algorithm Based on Dynamic Programming

Publications (Google Scholar Citations)

2024

• Gemini Team,
  Gemini 1.5: Unlocking Multimodal Understanding Across Millions of Tokens of Context,
  arXiv:2403.05530 [cs.CL], Mar. 2024.

2023

• Gemini Team,
  Gemini: A Family of Highly Capable Multimodal Models,
  arXiv:2305.10403 [cs.CL], Dec. 2023.
• Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi,
  Retrospective: A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing,
  ISCA-50 Retrospective: 1996-2020, Jun. 2023.
• Google,
  PaLM 2 Technical Report,
  arXiv:2305.10403 [cs.CL], May 2023.

2020

• Evan Z. Liu, Milad Hashemi, Kevin Swersky, Parthasarathy Ranganathan, and Junwhan Ahn,
  An Imitation Learning Approach for Cache Replacement,
  in Proceedings of the International Conference on Machine Learning (ICML), Jul. 2020.

2019

• Andres Lagar-Cavilla, Junwhan Ahn, Suleiman Souhlal, Neha Agarwal, Radoslaw Burny, Shakeel Butt, Jichuan Chang, Ashwin Chaugule, Nan Deng, Junaid Shahid, Greg Thelen, Kamil Adam Yurtsever, Yu Zhao, and Parthasarathy Ranganathan,
  Software-Defined Far Memory in Warehouse-Scale Computers,
  in Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Apr. 2019.
  Featured by The Morning Paper.

2018

• Mungyu Son, Junwhan Ahn, and Sungjoo Yoo,
  Non-Volatile Write Buffer-Based Journaling Bypass for Storage Write Reduction in Mobile Devices,
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, pp. 1747–1759, Sep. 2018.
• Namhyung Kim, Junwhan Ahn, Kiyoung Choi, Daniel Sanchez, Donghoon Yoo, and Soojung Ryu,
  Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture for Manycore Systems,
  ACM Transactions on Architecture and Code Optimization, vol. 15, pp. 10:1–10:23, Mar. 2018.
• Dongyoung Kim, Junwhan Ahn, and Sungjoo Yoo,
  ZeNA: Zero-Aware Neural Network Accelerator,
  IEEE Design & Test, Special Issue on Hardware Accelerators for Data Centers, vol. 35, pp. 39–46, Feb. 2018.

2017

• Eunhyeok Park, Junwhan Ahn, and Sungjoo Yoo,
  Weighted-Entropy-based Quantization for Deep Neural Networks,
  in Proceedings of the Conference on Computer Vision and Pattern Recognition (CVPR), Jul. 2017.
• Mungyu Son, Hyunsun Park, Junwhan Ahn, and Sungjoo Yoo,
  Making DRAM Stronger Against Row Hammering,
  to appear in Proceedings of the Design Automation Conference (DAC), Jun. 2017.
• Dongyoung Kim, Junwhan Ahn, and Sungjoo Yoo,
  A Novel Zero Weight/Activation-Aware Hardware Architecture of Convolutional Neural Network,
  in Proceedings of the Design, Automation, and Test in Europe (DATE), Mar. 2017.

2016

• Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi,
  AIM: Energy-Efficient Aggregation inside the Memory Hierarchy,
  ACM Transactions on Architecture and Code Optimization, vol. 13, pp.34:1–34:24, Oct. 2016.
  Presented at the HiPEAC conference, Jan. 2017.
• Hyunsun Park, Dongyoung Kim, Junwhan Ahn, and Sungjoo Yoo,
  Zero and Data Reuse-aware Fast Convolution for Deep Neural Networks on GPU,
  in Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct. 2016.
• Sungkwang Lee, Taemin Lee, Hyunsun Park, Junwhan Ahn, Sungjoo Yoo, Youjip Won, and Sunggu Lee,
  Differential Write-Conscious Software Design on Phase-Change Memory: An SQLite Case Study,
  ACM Transactions on Design Automation of Electronic Systems, vol. 21, pp. 47:1–47:25, Apr. 2016.
• Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi,
  Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture,
  IEEE Transactions on Computers, vol. 65, pp. 940–951, Mar. 2016.
• Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi,
  Low-Power Hybrid Memory Cubes with Link Power Management and Two-Level Prefetching,
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, pp. 453–464, Feb. 2016.

2015

• Namhyung Kim, Junwhan Ahn, Woong Seo, and Kiyoung Choi,
  Energy-Efficient Exclusive Last-Level Hybrid Caches Consisting of SRAM and STT-RAM,
  in Proceedings of the International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2015.
• Hyunsun Park, Junwhan Ahn, Eunhyeok Park, and Sungjoo Yoo,
  Locality-Aware Vertex Scheduling for GPU-based Graph Computation,
  in Proceedings of the International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2015.
• Mungyu Son, Junwhan Ahn, and Sungjoo Yoo,
  A Tiny-Capacitor-backed Non-Volatile Buffer to Reduce Storage Writes in Smartphones,
  in Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct. 2015.
• Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi,
  PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture,
  in Proceedings of the International Symposium on Computer Architecture (ISCA), Jun. 2015.
• Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi,
  A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing,
  in Proceedings of the International Symposium on Computer Architecture (ISCA), Jun. 2015.
  Selected as an Honorable Mention in the IEEE Micro Top Picks 2015.
  Selected for inclusion in ISCA-50 25-year Retrospective 1996-2020.
• Eunhyeok Park, Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, and Sunggu Lee,
  Memory Fast-Forward: A Low Cost Special Function Unit to Enhance Energy Efficiency in GPU for Big Data Processing,
  in Proceedings of the Design, Automation, and Test in Europe (DATE), Mar. 2015.
• Jinho Lee, Junwhan Ahn, Kiyoung Choi, and Kyungsu Kang,
  THOR: Orchestrated Thermal Management of Cores and Networks in 3D Many-Core Architectures,
  in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2015.

2014

• Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi,
  Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes,
  in Proceedings of the Design Automation Conference (DAC), Jun. 2014.
• Junwhan Ahn and Kiyoung Choi,
  LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology,
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, pp. 1197–1201, May 2014.
• Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi,
  DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture,
  in Proceedings of the International Symposium on High Performance Computer Architecture (HPCA), Feb. 2014.

2013

• Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi,
  Write Intensity Prediction for Energy-Efficient Non-Volatile Caches,
  in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), Sep. 2013.
• Kyuseung Han, Junwhan Ahn, and Kiyoung Choi,
  Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA,
  ACM Transactions on Architecture and Code Optimization, vol. 10, pp. 8:1–8:25, May 2013.
• Junwhan Ahn, Sungjoo Yoo, and Kiyoung Choi,
  Selectively Protecting Error-Correcting Code for Area-Efficient and Reliable STT-RAM Caches,
  in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2013.
• Junwhan Ahn and Kiyoung Choi,
  Isomorphism-Aware Identification of Custom Instructions with I/O Serialization,
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, pp. 34–46, Jan. 2013.

2012

• Di Wu, Junwhan Ahn, Imyong Lee, and Kiyoung Choi,
  Resource-shared Custom Instruction Generation under Performance/Area Constraints,
  in Proceedings of the International Symposium on System-on-Chip (SOC), Oct. 2012.
• Junwhan Ahn and Kiyoung Choi,
  Lower-Bits Cache for Low Power STT-RAM Caches,
  in Proceedings of the International Symposium on Circuits and Systems (ISCAS), May 2012.

2011

• Junwhan Ahn and Kiyoung Choi,
  An Efficient Algorithm for Isomorphism-Aware Custom Instruction Identification for Extensible Processors,
  in Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct. 2011.
• Di Wu, Imyong Lee, Junwhan Ahn, and Kiyoung Choi,
  Fast Generation of Multiple Custom Instructions under Area Constraints,
  Journal of Semiconductor Technology and Science, vol. 11, pp. 51–58, Mar. 2011.
• Junwhan Ahn, Imyong Lee, and Kiyoung Choi,
  A Polynomial-Time Custom Instruction Identification Algorithm Based on Dynamic Programming,
  in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2011.
  Nominated for Best Paper Award.

Invited Talks, Posters, and Others

• Architectural Techniques for Memory Systems based on Emerging Memory Technologies,
  Student Poster Session at HiPEAC 2017, Stockholm, Sweden, Jan. 2017.
• STT-RAM Cache Architectures for Low Power and Reliability,
  Asian Non-Volatile Memory Workshop (ANVMW), Beijing, China, Jul. 2012.
• LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology,
  Design Automation Conference (DAC) Work-in-Progress Forum, San Francisco, CA, USA, Jun. 2012.
• Efficient Approaches to Custom Instruction Identification for Extensible Processors,
  ACM Student Research Competition at DAC, San Diego, CA, USA, Jun. 2011.

Awards and Honors

• ISCA-50 25-year Retrospective 1996-2020 · 2023
• Deputy Prime Minister's Commendation for Outstanding BK21+ Graduate Student, Ministry of Education · 2017
• Distinguished Dissertation Award, Department of ECE, Seoul National University · 2017
• Gold Prize (co-author), Samsung HumanTech Paper Award · 2017
• Outstanding Graduate Student Award, Department of ECE, Seoul National University · 2017
• Gold Prize, Samsung HumanTech Paper Award · 2016
• IEEE Micro Top Picks Honorable Mention · 2016
• Semi-Finalist, ACM Student Research Competition at DAC · 2011
• Best Paper Award Nomination, Asia and South Pacific Design Automation Conference (ASP-DAC) · 2011
• National Science and Technology Scholarship · 2007–2010